Noise improvements in transistors



March 15, 1966 H?. FISCHLER NOISE IMPROVEMENTS IN TRANSISTORS Filed July 20, 1961 Fr-. Z

United States Patent O 3,241,083 NISE IMPROVEMENTS IN rITRANSISTRS Henryk Fischler, Tel-Aviv, Israei, assigner to The Weizmann Institute of Science, Rehovoth, Israel Fiied July 20, 1961, Ser. No. 125,532 1 Claim. (Cl. 33o-4%) My invention relates to D.C. bias networks, and more particularly for low level transistor amplifier stages when high input impedance is required.

As is well known, the noise figure, i.e., the ratio of noise to signal level N/S of the entire amplifier is a function of the noise engendered in the input of the first stage of the ampliiie-r. In such a case, the noise obtains the same ratio of gain as does the desired signal.

It is accordingly desirable to reduce the noise at the input of the tirst stage in order to maintain the smallest N/S ratio.

Noise, created by the `transistor itself, is also produced by resistors used in the amplifier. Present commercially available resisto-rs of high values are of carbon composition or film types and generate noise not only of resistance thermal character (Iohnson noise), but also arising from the resistance uctuation. 'Ihis second kind of noise occurs when current ilows through the resistor and among other features it increases with increasing resistance and with increased load current. Resistors, however, are essential for providing the required bias potentials at the electrodes of the transistors as well as the necessary high impedance for large gain of the amplilier.

I have discovered a network arrangement by which I can achieve both high impedance and the necessary bias potentials with substantially less resistances than has heretofore been required.

Accordingly, an object of my invention is to provide a novel circuit arrangement for providing bias potentials.

Another object of my invention is to provide a novel bias networks having components of relatively low resistance.

Still a further object of my invention is to provide a novel low noise transistor ampliier having large input impedance.

These and other objects of my invention will become evident from the following drawings in which:

FIGURE 1 is a circuit diagram of one embodiment of my invention.

FIGURE 2 is a circuit diagram showing an alternate embodiment of my invention.

FIGURES 3 and 4 show conventional prior art circuit diagrams; and

FIGURE 5 is a circuit diagram showing my novel network applied to an amplifier transmitter system.

Referring to FIGURES l and 2, my novel bias networks have one common relatively large resistor R21 (FIGURE 1) and R21 (FIGURE 2) for the forward and reverse bias paths, and two relatively small resistors R11, R31 and R12, R32 each in one of the bias paths, enabling the control of the working point of the transistor, together with the possibility of reversing the direction of the bias current and the control of degree of D.C. bias stability, as in the conventional bias networks.

In the prior art shown in FIGURE 3, two relatively large resistors R13 and R23 are connected as a voltage divider. The voltage at the junction of R13 and R13 is determined by the ratio of these resistors and is applied as the bias voltage to the base of the transistor.

The desired ratios of resistors may be obtained over almost any range of resistance value. However, in order to achieve a high input impedance, the resistors R13 and therefore R13 are made relatively large.

Such large resistors necessarily mean large noise factors which are undesirable.

I have discovered that by separating the functions of the resistors to provide bias on the one hand, and to provide high input impedance, on the other hand, I can achieve both the required high input impedance and the required bias with -rnuch smaller values of resistors.

In accordance with this novel principle, the two resistors R11 and R11 (FIGURE 1) are connected as a voltage divider in substantially the same ratio relation as the resistors R13 and R13 in FIGURE 3. There is however Vthis basic diference, ie. the resistors 13 and 23` FIGURE 3 are relatively larger resistors whereas R11 and R31 are relatively small resistors.

However, such low resistors by themselves do not provide the necessary high input impedance. To provide this, a relatively large resistor R21 FIGURE 1 extends from the junction of R11 and R31 to the base electrode 2 of the transistor.

In FIGURE 1, a resistor R11 extends between one side 3 of source of power and the collector electrode 4 of a transistor 12 and a resistor RE1 extends between the emitter 5 of transistor L2 and the other side of the source of power.

By proper design, the values of R11, R31 and R21 can be so predetermined that the required bias voltage is obtained at net resistance value less than that required in FIGURE 3 for R13 and R23 in a transistor amplifier having high input impedance.

The common and relatively larger resistor R21 which provides high impedance is chosen close to the value of the resulting bias resistance desired in order to obtain the optimal values of the other two resistors R11 and R31.

The value for R11 is computed from the equation:

RU: Vbat l Rres I R2l) Bi'Rres 1+ (Vani 'i- Vm) The value for R31 is computed from the equation:

R31: Vhut l(Rres I RZI) Vim 1-iIBrRi-es ii-(VEBV-VEO] In these equations:

1ll'll Rres l RZI+RH+R31 and Vba11 is the voltage of the bias voltage supply; R31 is the resistance in the current path 1131; VEB1 is the emitter-to-base voltage and V111 the voltage appearing across the resistor R111.

The network of FIGUR'E 2 may similarly be determined by a resistor value for VCG2 (Rres 2 R22) R32 VCGZ (Rres 2- R22) after the value of R11 has been chosen.

Limitation for the use of the new bias networks are expressed by the formulae for the bias base current, IB

res 1 9 o impedance of the transistor itself (as can be seen from FIG. 1).

which constitutes the Equation 2 above.

In a similar manner, from FIG. 2, the Equations 4 and 5 above can be derived:

The resulting resistance of the bias configuration (neglecting R12 as a relative small component) which shunts the input impedance of the transistor itself.

Substituting successively Equations 16 and 14 into 13, we obtain VCG2 Rres 2 R22) which constitutes the Equation 5.

The Equations 1 and 2 have a real meaning for positive denominators only. Thus Bringing down IB1 from Equations 19 and 20 and taking those together, the Equation 6 is obtained.

Similarly, the Equations 4 and 5 have a real meaning for positive denominators only. Thus IB2'Rres 2+(VEB2+VE2) 0 (2l) VcGa- [lBzRres 2-1-(VEB2-l-VE2N20 (22) Bringing down IB2 from Equations 21 and 22 and taking those together, the Expression 7 is obtained (Voz: VcGz- Vnz as it can be seen from FIG. 2).

Practically the working point for the low noise high input impedance stage can always be chosen in these limits, lthe supply voltage being here the significant factor.

Examples of such values are as follows:

To obtain the resultant resistance of the bias network of about 500 kilohms in a particular transistor stage in the collector-grounded configuration (RL=0), working at collector current Ic=0.07 ma. and collector-to-emitter voltage VCE of 1.2 v., at 2.6 v. supply voltage:

For the conventional bias network, resistance Values used are:

R13 (and R1.1)=1.8 megohm, leading 0.7ua. R23 (or R24) :680 kilohm, leading 2.1 aa.

For the new bias network R11 (and R12) :82 kilohm, leading 20 fra.

R31 (and R32) :39 kilohm, leading 21.5 1a.

R21 (and R22)=470 kilohm, being the main factor of noise, leading 1.5 aa. It will be noted here that the current flow in R21 is exceedingly small.

In the same circuits, also of 500 kilohms resultant resistance of the bias network working at IC=0.1 ma., VC=O-8 v. at 2.6 v. supply;

For the conventional bias network are used R13 (or R1.1)=1 megohrn., leading 0.8 fra. R23 (or R21)=1 megohm, leading 1.8 ua.

For the new bias network R11 (or R12)=56 kilohm, leading 23 ,u.a.

R31 (or R32)=56 kilohm, leading 24 ua.

R21 (or R22) :470 kilohm, being the main factor or noise,

leading 1 ua.

From the above, it will now be clear that the improvement of the new bias networks consists of enabling the use, at the same operating point of the transistor, as for la conventional network, of bias resistors of smaller values -to achieve almost the same resulting resistance of the bias network. Therefore the same degree of D.C. bias stability and the same input impedance of -the stage, both being dependen-t on the resulting resistance of the bias network `are obtained as in the conventional circuit. The bias resistors of smaller values contribute in their final configuration to lower noise arising from the resistance fluctuations. Also the current flowing through the big common resistor, being yet the m-ain source of noise, is smaller than that which would flow in one of the bigger resistors in the conventional circuit, and so the noise from this resistor is smaller. As a result, the over-all noise from -the input of the stage is smaller than for a stage with the equivalent (as regard-ing working point, degree of D.C. bias stabili-ty and input impedance) conventional bias network.

In FIGURE 5, I have an amplifier circuit in which the novelty bias network is shown in one application thereof. As shown, the novel networks connected on the input of lthe first stage of the amplifier reduces the noise factor of this stage and thus reduces the total noise. The output of the amplifier is connected to the transmitter in conventional manner.

In FIGURE 5, an lactual circuit with values as used in one embodiment is shown. The amplifier 41 is shovm with the voltage dividers and high impedances corresponding Ito R31, R11 and R21 of FIGURE 1. 'Ihe input at 40 is connected directly to the base electrode of the transistor. Output signals from amplifier 41 are irnpressed across and modulate signals `from the oscillator and then are transmitted by transmitter 42.

I claim:

In a transistor circuit, -a source of bias potential, a voltage divider resistor network comprising a pair of resistors connected across said source of bias potential, a transistor having an input base electrode, an input circuit connected directly to said input base electrode, said transistor 'further having an emitter electrode which includes an emitter resistance connecting said emitter to said bias source, the natio of the respective resistance values of said pair being determined in accordance with the desired bias potenti-al and a resistance of relatively large value with respect to ,the value of each of said pair of resistances extending vfrom the junction of said resistors of said voltage divider network to the input electrode of said transistor, said resistance of relatively large value being chosen close `to the desired value of the resulting bias resistance which includes the said epair of resistors and said resistor of relatively lange value to obtain optimal values of each of said pair of resistors, and the values of `the resistance of the voltage divider being chosen in accordance with the equations:

Vbab 1(Rres l-RZI) and where R11 yand R31 are the resistors of the voltage divider, Vm, 1 is the voltage of said source of bias voltage, R21 is the value of resistance of said relatively large VEB1+VE1 IB1 V1M 1 (VEBi-l-VE1) 4) Rres 1 Rrcs 1 whereby a reduction of noise level is produced.

References Cited by the Examiner UNITED STATES PATENTS 12/ 1963 Barter.

OTHER REFERENCES MacDougall: Equations Speed Common Emitter Bias Design, Raytheon, File No. 154-T, December 1960.

Martin: Electronic Circuits, Prentice-Hall, Inc. 1955, sec. 9.13, pages 325, 244, Figure 9.9, Equation 9.36.

ROY LAKE, Primary Examiner.

ARTHUR GAUSS, NATHAN KAUFMAN, Examiners. 

